A non-volatile memory is a type of memory device that retains stored data when power is removed. There are various types of non-volatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is the flash EEPROM device (also referred to as “flash memory”)
Each non-volatile memory device has its own unique characteristics. For example, the memory cells of an EPROM device are erased using an ultraviolet light, while the memory cells of an EEPROM device are erased using an electrical signal. In a conventional flash memory device blocks of memory cells are simultaneously erased. The memory cells in a ROM device, on the other hand, cannot be erased at all. EPROMs, EEPROMs and flash memory are commonly used in computer systems that require reprogrammable non-volatile memory.
A conventional flash memory device includes a plurality of memory cells, each cell is provided with a floating gate covered with an insulating layer. There is also a control gate which overlays the insulating layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the cell substrate. This insulating layer is an oxide layer and is often referred to as the tunnel oxide. The substrate contains doped source and drain regions, with a channel region disposed between the source and drain regions.
In a flash memory device, a charged floating gate represents one logic state, e.g., a logic value “0,” while a non-charged floating gate represents the opposite logic state e.g., a logic value “1.” The flash memory cell is programmed by placing the floating gate into one of these charged states. A flash memory cell is un-programmed, or erased, when the charge is removed from the floating gate.
One method of programming a flash memory cell is accomplished by applying a known potential to the cell's drain and a programming potential to its control gate. This causes electrons to be transferred from the source to the floating gate of the memory cell. The programming action of transferring electrons to the floating gate results in a memory cell that conducts less current when read than it would otherwise in the un-programmed state.
Large negative voltages up to e.g., −9.5V are often used when erasing a flash memory cell. Once the erase operation is finished, the large negative voltage (VN) must be discharged to a ground potential (e.g., 0V) in a fixed period of time. Typically, an n-channel pull-down transistor is used to discharge the voltage VN. Because this n-channel “discharge” transistor will have the large negative voltage VN (e.g., −9.5V) across its source/drain terminals, the discharge transistor is prone to the phenomenon known as “snapback.” MOSFET snapback is typically defined as a phenomenon in which a MOSFET switches from a high voltage/low current state to a low voltage/high current state by activating the parasitic bipolar device between the MOSFET source, body and drain. A trigger voltage, Vt, is the voltage at which the regenerative effects associated with MOSFET snapback begin.
As is known in the art, a transistor is susceptible to snapback when it has a high field across it drain region (i.e., a large voltage across its source/drain). If the transistor is activated too quickly, snapback may occur. That is, snapback occurs when the parasitic bipolar transistor that exists between the source and drain (for ESD purposes) amplifies the current that results from activating the transistor. This snapback phenomenon results in a very high current between the source and drain regions of the transistor, which is undesirable and may alter the performance of the memory device.
U.S. Pat. No. 6,438,032, assigned to Micron Technology, Inc., and hereby incorporated by reference herein, discloses one technique for controlling a discharge transistor to avoid problems, such as snapback. FIG. 1 is an illustration of charge pump and discharge circuitry 50 incorporating the technique disclosed in the '032 patent. The circuitry 50 includes a charge pump 316, discharge control circuit 324, NMOS discharge transistor 288, discharge control capacitor 292, an NMOS transistor 286 and a PMOS transistor 218.
The charge pump 316 is responsible for generating an elevated erase voltage VN required for the erasure of non-volatile memory cells of the memory device containing the circuitry 50. The charge pump 316 is enabled by an active (i.e., high) erase signal ERASEP when the memory device containing circuitry 50 performs an erase operation. The erase voltage VN generated by the charge pump 316 is placed on signal output line 258, which is connected to an array of non-volatile memory cells (not shown in FIG. 1). After an erase operation takes place, the ERASEP signal transitions to inactive (i.e., low), deactivating the charge pump 316 and enabling the discharge control circuit 324.
The discharge control circuit 324 controls the discharge of the remaining voltage from the charge pump output 258 to ground through NMOS discharge transistor 288. Discharge transistor 288 is normally turned off by capacitor 292. During discharge, the gate of the discharge transistor 288 is raised by a discharge control signal DISCHARGE so that the transistor 288 operates in a linear region for a specified time period to discharge a portion of the pump voltage in a controlled, ramped manner before being driven into saturation to quickly discharge any remaining portion of the pump voltage.
The operation of the circuitry 50 is now described in slightly more detail. When the memory device performs an erase operation, the charge pump 316 is active and provides the erase voltage VN at signal output line 258. The charge pump 316, when active, turns on NMOS transistor 286, which couples circuit node 290 to the erase voltage VN on output line 258. The presence of the negative erase voltage VN on circuit node 290 ensures that the NMOS discharge transistor 288 is inactive and not conducting to ground while the charge pump 316 is active. Additionally, the coupling of the negative erase voltage VN to node 290 charges the discharge control capacitor 292 to the voltage VN. The charge pump 316, while active, also turns off PMOS transistor 218, which isolates the discharge control circuit 324 from circuit node 290 and the negative erase voltage VN.
After an erase operation, the ERASEP signal becomes inactive (low) and the charge pump 316 is deactivated. NMOS transistor 286 is turned off, isolating circuit node 290 from the voltage on the signal output line 258. At the same time, the PMOS transistor 218 is turned on, which couples the discharge control circuit 324 to circuit node 290, which is maintained at the negative erase voltage VN by the charged discharge control capacitor 292. The inactive (low) ERASEP signal also enables the discharge control circuit 324, which provides a control signal DISCHARGE (or current flow) to circuit node 290 through the PMOS transistor 218. This control signal DISCHARGE gradually charges the discharge control capacitor 292. As the discharge control capacitor 292 charges, the voltage signal on circuit node 290 gradually rises from the negative erase voltage VN to a supply voltage VCC. Circuit node 290 is coupled to the gate of the NMOS discharge transistor 288 and the rising voltage on circuit node 290 activates the discharge transistor 288 to slowly discharge the residual voltage from signal output line 258 and the disabled charge pump 316.
After discharge of the residual voltage from signal output line 258, the discharge control circuit 324 maintains a bias on the gate of the discharge transistor 288. This keeps the discharge transistor 288 enabled until the next erase operation.
Thus, as shown in FIG. 2, the '032 patent discloses activating the discharge transistor 288 (i.e., using the slowly ramping DISCHARGE control signal) over a period time Z (i.e., discharge time) to discharge the large negative erase voltage VN (e.g., −9.5V) to the ground potential (e.g., 0V). The inventors of the present invention have discovered that the snapback phenomenon depends on other factors, in addition to discharge time, such as the source/drain voltage across the discharge transistor 288. Thus, it is desirable to control the source/drain voltage across the discharge transistor 288 of a non-volatile memory device to substantially mitigate the effects of snapback and to improve the overall efficiency and operation of the memory device.